module register_element
(
	input wire sys_clk,
	input wire sys_rst_n,
	inout wire [15:0] ctrl_sig_inner,
	inout wire [15:0] addr_sig_inner,
	inout wire [15:0] data_sig_inner,
	inout wire work_ok_inner,
	output reg [15:0] data_reg
);

/************************************
inout wire wr_en:ctrl_sig_inner[0]
inout wire rd_en:ctrl_sig_inner[1]
************************************/

parameter REG_ID = 4'd0;

reg [15:0] data_sig_represent;
reg work_ok_represent;
reg get_time;
reg get_time_d1;
reg get_time_d2;
reg write_time;
reg write_time_d1;

wire [3:0] reg_id;

assign reg_id = REG_ID;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
		data_reg <= 16'h0;
	else if (ctrl_sig_inner[0] == 1'b1 && addr_sig_inner[3:0] == reg_id)
		data_reg <= data_sig_inner;
	else
		data_reg <= data_reg;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
		write_time <= 1'b0;
	else if (ctrl_sig_inner[0] == 1'b1 && addr_sig_inner[3:0] == reg_id)
		write_time <= 1'b1;
	else
		write_time <= 1'b0;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
		write_time_d1 <= 1'b0;
	else
		write_time_d1 <= write_time;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
		get_time <= 1'b0;
	else if (ctrl_sig_inner[1] == 1'b1 && addr_sig_inner[3:0] == reg_id)
		get_time <= 1'b1;
	else
		get_time <= 1'b0;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
	begin
		get_time_d1 <= 1'b0;
	end
	else
	begin
		get_time_d1 <= get_time;
	end

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
		data_sig_represent <= 16'hz;
	else if (get_time == 1'b1)
		data_sig_represent <= 16'h0;
	else if (get_time_d1 == 1'b1)
		data_sig_represent <= data_reg;	
	else
		data_sig_represent <= 16'hz;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
		work_ok_represent <= 1'bz;
	else if (write_time == 1'b1)
		work_ok_represent <= 1'b0;
	else if (write_time_d1 == 1'b1)
		work_ok_represent <= 1'b1;
	else if (get_time == 1'b1)
		work_ok_represent <= 1'b0;
	else if (get_time_d1 == 1'b1)
		work_ok_represent <= 1'b1;
	else
		work_ok_represent <= 1'bz;

assign data_sig_inner = data_sig_represent;
assign work_ok_inner = work_ok_represent;

endmodule







